Comparison of power consumption among asynchronous design styles with their synchronous counterparts

Midwest Symposium on Circuits and Systems

Volumn 1, Issue , 1994, Pages 7-10

  Kim, Seokjin ^a   Sridhar, Ramalingam ^a  

^a UNIVERSITY AT BUFFALO   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; COMPUTER SIMULATION; PARALLEL PROCESSING SYSTEMS; PROBABILITY; TIMING CIRCUITS;

ASYNCHRONOUS DESIGN; DATA PATH BLOCK; FOUR PHASE HANDSHAKING; POWER CONSUMPTION;

LOGIC DESIGN;

EID: 0028744749     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)