Parallel logic level simulation of VLSI circuits

Winter Simulation Conference Proceedings

Volumn , Issue , 1994, Pages 1354-1361

  Bagrodia, Rajive ^a   Li, Zheng ^a   Jha, Vikas ^a   Chen, Yuan ^a   Cong, Jason ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; COMPUTER PROGRAMMING LANGUAGES; COMPUTER SIMULATION; LOGIC PROGRAMMING; PARALLEL ALGORITHMS; SUPERCOMPUTERS;

ACYCLIC MULTIWAY NETWORK PARTITIONING ALGORITHM; ALGORITHM INDEPENDENT SIMULATION LANGUAGE; BOOLEAN NETWORKS; COMBINATIONAL BOOLEAN CIRCUITS; DISCRETE EVENT SIMULATION MODEL; PARALLEL LOGIC LEVEL SIMULATION;

VLSI CIRCUITS;

EID: 0028743710     PISSN: 02750708     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (18)