A 500 MHz, 32 bit, 0.4 µm CMOS RISC Processor

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 12, 1994, Pages 1464-1473

  Suzuki, Kazumasa ^a   Nakayama, Takashi ^a   Abiko, Hitoshi ^a   Ono, Atsuki ^a   Okabe, Kazuhiro ^a   Heiuchi, Hideki ^a   Goto, Junichi ^a   Inoue, Toshiaki ^a   Koseki, Youich ^a   Yamada, Hachiro ^a  

^a NEC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; ENERGY DISSIPATION; FREQUENCY MULTIPLYING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; PHASE LOCKED LOOPS; PIPELINE PROCESSING SYSTEMS; REDUCED INSTRUCTION SET COMPUTING; RESISTORS; TECHNOLOGY; TRANSISTORS;

DOUBLE STAGE BINARY LOOK AHEAD CARRY ADDER CIRCUIT; HIGH SPEED CIRCUITS; LOW VOLTAGE SWING INTERFACE CIRCUIT; SMALL SKEW CLOCK DISTRIBUTION; STACKED POWER LINE STRUCTURE;

MICROPROCESSOR CHIPS;

EID: 0028741478     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.340419     Document Type: Article

References (10)

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