Dual-state systolic architecture for recursive least-squares updating and downdating

IEEE Workshop on VLSI Signal Processing, Proceedings

Volumn , Issue , 1994, Pages 316-325

  Yang, T C ^a   Yao, K ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMPUTER ARCHITECTURE; DATA HANDLING; DATA STRUCTURES; ERROR ANALYSIS; LEAST SQUARES APPROXIMATIONS; MATHEMATICAL MODELS; RECURSIVE FUNCTIONS;

DUAL STATE SYSTOLIC ARRAY; ORTHOGONAL DOWNDATING; ORTHOGONAL UPDATING; RECURSIVE LEAST SQUARES;

DIGITAL SIGNAL PROCESSING;

EID: 0028737864     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)