Power and performance simulator: ESP and its application for 100MIPS/W class RISC design

IEEE Symposium on Low Power Electronics

Volumn , Issue , 1994, Pages 46-47

  Sato, Toshinori ^a   Nagamatsu, Masato ^a   Tago, Haruyuki ^a  

^a TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

INTEGRATED CIRCUIT LAYOUT; LSI CIRCUITS; MICROPROCESSOR CHIPS; OPTIMIZATION; PERFORMANCE; REDUCED INSTRUCTION SET COMPUTING;

LOW POWER DESIGN; POWER SIMULATOR EARLY DESIGN STAGE POWER (ESP);

DIGITAL INTEGRATED CIRCUITS;

EID: 0028737132     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/lpe.1994.573197     Document Type: Conference Paper

References (2)