Architectural performance verification: PowerPCTM processors

Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors

Volumn , Issue , 1994, Pages 344-347

  Surya, S ^a   Bose, P ^a   Abraham, J A ^a  

^a IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL LINGUISTICS; COMPUTER SIMULATION; COMPUTER SYSTEMS PROGRAMMING; CRITICAL PATH ANALYSIS; DATA STRUCTURES; ELECTRIC NETWORK PARAMETERS; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; PIPELINE PROCESSING SYSTEMS;

INSTRUCTION PER CYCLE; POWERPC PROCESSORS; STEADY STATE PARAMETER TESTING; TRANSIENT MODE TESTING;

PROGRAM PROCESSORS;

EID: 0028736773     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)