Chip scale package (CSP) 'a lightly dressed LSI chip'

Proceedings of the IEEE/CPMT International Electronics Manufacturing Technology (IEMT) Symposium

Volumn 1, Issue , 1994, Pages 169-176

  Yasunaga, Masatoshi ^a   Baba, Shinji ^a   Matsuo, Mitsuyasu ^a   Matsushima, Hironori ^a   Nakao, Shin ^a   Tachikawa, Toru ^a  

^a MITSUBISHI ELECTRIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRONICS PACKAGING; INTEGRATED CIRCUIT TESTING; MULTICHIP MODULES; SOLDERED JOINTS; SOLDERING; STANDARDIZATION; SURFACE MOUNT TECHNOLOGY; VINYL RESINS;

BARE CHIP FEATURE; CHIP SCALE PACKAGE; ELECTRODE PADS; EXTERNAL ELECTRODE BUMP; SINGLE CHIP PACKAGING;

LSI CIRCUITS;

EID: 0028736573     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (14)