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Volumn , Issue , 1994, Pages 69-84
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Influence of tester parasitics on 'charged device model' - failure thresholds
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Author keywords
[No Author keywords available]
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Indexed keywords
CALIBRATION;
CMOS INTEGRATED CIRCUITS;
ELECTRIC DISCHARGES;
ELECTRIC FAULT CURRENTS;
ELECTRIC IMPEDANCE;
ELECTRIC LINES;
ELECTRONICS PACKAGING;
INTEGRATED CIRCUIT LAYOUT;
MEASUREMENTS;
RELIABILITY;
ROBOTICS;
TRANSIENTS;
CHARGED DEVICE MODEL;
ELECTROSTATIC DISCHARGE;
ELECTROSTATIC POTENTIAL;
FAILURE THRESHOLDS;
TESTER PARASITICS;
ELECTRON DEVICE TESTING;
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EID: 0028735259
PISSN: 07395159
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
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Times cited : (33)
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References (26)
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