Delay-fault testability preservation of the concurrent decomposition and factorization transformations

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 15-21

  El Maleh, Aiman ^a   Rajski, Janusz ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT TESTING; LOGIC CIRCUITS; MATHEMATICAL TRANSFORMATIONS;

CONCURRENT DECOMPOSITION; DELAY FAULT TESTABILITY PRESERVATION; FACTORIZATION TRANSFORMATIONS;

LOGIC DESIGN;

EID: 0028734361     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)