Three-pattern tests for delay faults

Proceedings of the IEEE VLSI Test Symposium

Volumn , Issue , 1994, Pages 452-456

  Franco, Piero ^a   McCluskey, Edward J ^a  

^a STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; ELECTRIC FAULT CURRENTS; HAZARDS AND RACE CONDITIONS; MATHEMATICAL MODELS;

DELAY FAULT TESTING; GATE DELAY MODELS; THREE PATTERN TESTS;

INTEGRATED CIRCUIT TESTING;

EID: 0028733936     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (22)