A Quadruple Well, Quadruple Polysilicon BiCMOS Process for Fast 16 Mb SRAM’s

IEEE Transactions on Electron Devices

Volumn 41, Issue 12, 1994, Pages 2318-2325

  Hayden, James D ^a   Taft, C ^a   Mazure, C ^a   Gunderson, C ^a   Nguyen, B Y ^a   Woo, M ^a   Roman, Bernard J ^a   Radhakrishna, S ^a   Subrahmanyan, R ^a   Sitaram, A R ^a   Pelley, P ^a   Lin, J H ^a   Kemp, Kevin ^a   Kirsch, H ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; MOSFET DEVICES; OPTIMIZATION; PHASE SHIFT; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR STORAGE; THIN FILM DEVICES;

PELOX ISOLATION; QUADRUPLE WELL, QUADRUPLE POLYSILICON BICMOS PROCESS; SOFT ERROR RATE;

RANDOM ACCESS STORAGE;

EID: 0028731071     PISSN: 00189383     EISSN: 15579646     Source Type: Journal    
DOI: 10.1109/16.337444     Document Type: Article

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