A chip set for pipeline and parallel pipeline FFT architectures

Journal of VLSI Signal Processing

Volumn 8, Issue 3, 1994, Pages 253-265

  Szwarc, V ^a   Desormeaux, L ^a   Wong, W ^b   Yeung, C P S ^b   Chan, C H ^b   Kwasniewski, T A ^b  

^a Industry Canada   (Canada)

^b CARLETON UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL ARITHMETIC; FAST FOURIER TRANSFORMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; TREES (MATHEMATICS);

BOOTH ALGORITHM; BUILT IN SELF TEST; CASCADEABLE CHIPS; CHIP-INTERCONNECTIVITY; COMPLEX BUTTERFLY; REDUNDANT BINARY ARITHMETIC; WALLACE TREE;

MICROPROCESSOR CHIPS;

EID: 0028729018     PISSN: 09225773     EISSN: 1573109X     Source Type: Journal    
DOI: 10.1007/BF02106450     Document Type: Article

References (20)

1. A pipeline Fast Fourier Transform
2. Parallelism in Fast Fourier Transform Hardware
3. Parallel pipeline fast Fourier transformer
4. Pipeline and Parallel-Pipeline FFT Processors for VLSI Implementations
5. A 256-Point Discrete Fourier Transform Processor Fabricated in a 2 μm NMOS Technology
6. High Speed FFT Processor Implementation
7. A Self-Testing 2- μm CMOS chip set for FFT applications
8. A 70 MHz 1.2- μm CMOS 16-Point DFT Processor
9. A Wafer-Scale 170,000-Gate FFT Processor with Built-in Test Circuits
10. Signed-Digit Number Representations for Fast Parallel Arithmetic
11. A radix 4 delay commutator for Fast Fourier Transform processor implementation
12. Self-test: the solution to the VLSI test problem?