Testability considerations in technology mapping

Proceedings of the Asian Test Symposium

Volumn , Issue , 1994, Pages 151-156

  Pomeranz, Irith ^a   Reddy, Sudhakar M ^a  

^a UNIVERSITY OF IOWA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DYNAMIC PROGRAMMING; ITERATIVE METHODS; LOGIC GATES; MAPPING; OPTIMIZATION; TABLE LOOKUP; TECHNOLOGY; TREES (MATHEMATICS);

CONFIGURATION LOGIC BLOCKS; DESIGN FOR TESTABILITY; FIELD PROGRAMMABLE GATE ARRAYS; MAPPED CIRCUITS; TECHNOLOGY MAPPING;

INTEGRATED CIRCUIT TESTING;

EID: 0028727437     PISSN: 10817735     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)