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Volumn 41, Issue 6, 1994, Pages 2244-2251

Single Event Upsets in Gallium Arsenide Dynamic Logic

Author keywords

[No Author keywords available]

Indexed keywords

CHARGE CARRIERS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; FIELD EFFECT TRANSISTORS; FREQUENCY RESPONSE; GATES (TRANSISTOR); IONS; LOGIC CIRCUITS; PHASE MEASUREMENT; RADIATION EFFECTS; SPACE APPLICATIONS; VOLTAGE MEASUREMENT;

EID: 0028720643     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.340571     Document Type: Article
Times cited : (3)

References (18)
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  • 2
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    • Zdebel, P.J.1
  • 3
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    • Radiation Effects in GaAs Integrated Circuits: A Comparison with Silicon
    • Oct.
    • M. Simons, “Radiation Effects in GaAs Integrated Circuits: A Comparison with Silicon,” 5th Annual IEEE GaAs IC Symp. Tech. Digest, pp. 2–6, Oct. 1983.
    • (1983) 5th Annual IEEE GaAs IC Symp. Tech. Digest , pp. 2-6
    • Simons, M.1
  • 6
    • 0026941657 scopus 로고
    • GaAs Two-Phase Dynamic FET Logic: A Low-Power Logic Family for VLSI
    • Oct.
    • K. R. Nary and S. I. Long, “GaAs Two-Phase Dynamic FET Logic: A Low-Power Logic Family for VLSI,” IEEE J. Solid-State Circuits, Vol. 27, No. 10, pp. 1364–1371, Oct. 1992.
    • (1992) IEEE J. Solid-State Circuits , vol.27 , Issue.10 , pp. 1364-1371
    • Nary, K.R.1    Long, S.I.2
  • 8
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    • L. Yang, R. Chakharapani, and S. I. Long, “A High-Speed Speed Dynamic Domino Circuit Implemented with GaAs MESFET’s,” IEEE J. Solid-State Circuits, Vol. SC-22, No. 5, pp. 874–879, Oct. 1987.
    • (1987) IEEE J. Solid-State Circuits , vol.SC-22 , Issue.5
    • Yang, L.1    Chakharapani, R.2    Long, S.I.3
  • 9
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    • Dynamic GaAs Capacitively Coupled Domino Logic (CCDL)
    • Jun.
    • D. H. K. Hoe and C. A. T. Salama, “Dynamic GaAs Capacitively Coupled Domino Logic (CCDL),” IEEE J. Solid-State Circuits, Vol. 26, No. 6, pp. 844–849, Jun. 1991.
    • (1991) IEEE J. Solid-State Circuits , vol.26 , Issue.6 , pp. 844-849
    • Hoe, D.H.K.1    Salama, C.A.T.2
  • 10
    • 4243178145 scopus 로고
    • A 1 mW, 500 MHz, 4-Bit Adder Using Two-Phase Dynamic FET Logic Gates
    • Oct.
    • K. R. Nary and S. I. Long, “A 1 mW, 500 MHz, 4-Bit Adder Using Two-Phase Dynamic FET Logic Gates,” 14th Annual IEEE GaAs IC Symp. Tech. Digest, pp. 97–100, Oct. 1992.
    • (1992) 14th Annual IEEE GaAs IC Symp. Tech. Digest , pp. 97-100
    • Nary, K.R.1    Long, S.I.2
  • 11
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    • (1988) IEEE Trans. Nuc. Sci , vol.35 , Issue.6 , pp. 1517-1522
    • Buchner, S.1    Knudson, A.2    Kang, K.3    Campbell, A.B.4
  • 13
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    • McMorrow, D.1    Knudson, A.2    Campbell, A.B.3
  • 18
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.