Planar-DME: Improved planar zero-skew clock routing with minimum pathlength delay

European Design Automation Conference - Proceedings

Volumn , Issue , 1994, Pages 440-445

  Kahng, Andrew B ^a   Tsao, Chung Wen Albert ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; ELECTRIC NETWORK SYNTHESIS; ELECTRIC NETWORK TOPOLOGY; ELECTRIC WIRING; MICROPROCESSOR CHIPS; MINIMIZATION OF SWITCHING NETS; TREES (MATHEMATICS);

CLOCK ROUTING; CLOCK TREES; TOP DOWN ALGORITHM;

INTEGRATED CIRCUIT LAYOUT;

EID: 0028714355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)