Novel high-speed latching operation flip-flop (HLO-FF) circuit and its application to a 19 Gb/s decision circuit using 0.2 μm GaAs MESFET

Technical Digest - GaAs IC Symposium (Gallium Arsenide Integrated Circuit)

Volumn , Issue , 1994, Pages 193-196

  Murata, K ^a   Otsuji, T ^a   Ohhata, M ^a   Togashi, M ^a   Sano, E ^a   Suzuki, M ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; DELAY CIRCUITS; ELECTRIC CURRENTS; ELECTRIC RESISTANCE; EQUIVALENT CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOGIC CIRCUITS; LOGIC GATES; MESFET DEVICES; OPTIMIZATION; PARAMETRIC DEVICES; SEMICONDUCTING GALLIUM ARSENIDE;

ANALYTICAL DELAY TIME; DECISION CIRCUIT; GATE WIDTH RATIO; LATCHING CIRCUITS; LATCHING OPERATION; MASTER LATCH; SERIES GATE CIRCUITS; SPICE SIMULATION; SWITCHING CURRENTS;

FLIP FLOP CIRCUITS;

EID: 0028714060     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)