Performance evaluator for parameterized ASIC architectures

European Design Automation Conference - Proceedings

Volumn , Issue , 1994, Pages 66-71

  Gong, Jie ^a   Gajski, Daniel D ^a   Nicolau, Alex ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ELECTRIC NETWORK PARAMETERS; INTEGRATED CIRCUITS; LOGIC DESIGN; MATHEMATICAL MODELS; PARALLEL PROCESSING SYSTEMS; PROGRAM COMPILERS; SCHEDULING; STATE ASSIGNMENT; SYSTEMS ANALYSIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS (ASICS); ULTRA FINE GRAIN SCHEDULER;

COMPUTER ARCHITECTURE;

EID: 0028713841     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)