Perturb and simplify: multi-level boolean network optimizer

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 2-5

  Chang, Shih Chieh ^a   Marek Sadowska, Malgorzata ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BOOLEAN ALGEBRA; COMPUTATIONAL METHODS; ELECTRIC NETWORK ANALYSIS; FUNCTION EVALUATION; HEURISTIC METHODS; LOGIC DESIGN; LOGIC GATES; MINIMIZATION OF SWITCHING NETS; OPTIMIZATION; REDUNDANCY;

ABSOLUTE DOMINATORS; AUTOMATIC TEST PATTERN GENERATION; LOGIC FUNCTIONALITY CHANGE; MULTI LEVEL BOOLEAN NETWORK OPTIMIZERS; WIRE SUBSTITUTION PROCEDURE;

COMBINATORIAL CIRCUITS;

EID: 0028712931     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)