Macromodeling of analog circuits for hierarchical circuit design

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn , Issue , 1994, Pages 656-664

  Shao, Jianfeng ^a   Harjani, Ramesh ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANALOG TO DIGITAL CONVERSION; APPROXIMATION THEORY; DIGITAL CIRCUITS; EVALUATION; HIERARCHICAL SYSTEMS; INTEGRATED CIRCUIT LAYOUT; LINEAR INTEGRATED CIRCUITS; PERFORMANCE; SEMICONDUCTOR DEVICE MODELS;

ANALOG CIRCUITS; HIERARCHICAL CIRCUIT DESIGN; LAYERED VOLUME SLICING METHODOLOGY; MACROMODELING; SUB BLOCK DESIGN;

ELECTRIC NETWORK SYNTHESIS;

EID: 0028712703     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (13)