메뉴 건너뛰기




Volumn 41, Issue 6, 1994, Pages 2026-2034

Single Event Mirroring and DRAM Sense Amplifier Designs for Improved Single-Event-Upset Performance

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); BIT ERROR RATE; CAPACITANCE; CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC CHARGE; RADIATION EFFECTS; RADIATION PROTECTION; RESISTORS; TRANSISTORS;

EID: 0028705537     PISSN: 00189499     EISSN: 15581578     Source Type: Journal    
DOI: 10.1109/23.340538     Document Type: Article
Times cited : (8)

References (25)
  • 2
    • 0026103180 scopus 로고
    • Ion Microprobing of Sense Amplifiers to Analyze Single Event Upsets in a CMOS DRAM
    • Feb.
    • L.M.Geppert, U.Bapst, D.F.Heidel, and K.A.Jenkins, “Ion Microprobing of Sense Amplifiers to Analyze Single Event Upsets in a CMOS DRAM,” IEEE Journal of Solid-State Circuits, Vol. 26, No. 2, pp.132, Feb. 1991
    • (1991) IEEE Journal of Solid-State Circuits , vol.26 , Issue.2 , pp. 132
    • Geppert, L.M.1    Bapst, U.2    Heidel, D.F.3    Jenkins, K.A.4
  • 3
    • 0026896296 scopus 로고
    • Experimental Investigation of the Minimum Signal for Reliable Operation of DRAM Sense Amplifiers
    • July
    • H.Geib et. al., “Experimental Investigation of the Minimum Signal for Reliable Operation of DRAM Sense Amplifiers,” IEEE Journal of Solid-State Circuits, Vol.27, No.7, pp.1028, July 1992
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.7 , pp. 1028
    • Geib, H.1
  • 5
    • 0020904494 scopus 로고
    • Charge Collection in Test Structures
    • Dec.
    • A.B.Campbell et al., “Charge Collection in Test Structures,” Vol. NS30, No. 6, pp. 4486, Dec. 1983
    • (1983) , vol.NS30 , Issue.6 , pp. 4486
    • Campbell, A.B.1
  • 6
    • 0026373079 scopus 로고
    • SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder
    • Dec.
    • S.Whitaker, J.Canaris and K.Liu, “SEU Hardened Memory Cells for a CCSDS Reed Solomon Encoder,” IEEE Transactions of Nuclear Science, Vol. NS38, No. 6, pp. 1471, Dec.1991
    • (1991) IEEE Transactions of Nuclear Science , vol.NS38 , Issue.6 , pp. 1471
    • Whitaker, S.1    Canaris, J.2    Liu, K.3
  • 7
    • 0020311020 scopus 로고
    • Single Event Error Immune CMOS RAM
    • Dec.
    • J.L.Andrew et. al., “Single Event Error Immune CMOS RAM,” IEEE Trans. of Nuclear Science, Vol. NS29, No. 6, pp. 2040, Dec.1982
    • (1982) IEEE Trans. of Nuclear Science , vol.NS29 , Issue.6
    • Andrew, J.L.1
  • 8
    • 0020247202 scopus 로고
    • Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs
    • Dec.
    • S.E.Diehl et. al., “Error Analysis and Prevention of Cosmic Ion-Induced Soft Errors in Static CMOS RAMs,” IEEE Transactions of Nuclear Science, Vol. NS29, No. 6, pp. 2032, Dec.1982
    • (1982) IEEE Transactions of Nuclear Science , vol.NS29 , Issue.6
    • Diehl, S.E.1
  • 9
    • 0023589974 scopus 로고
    • An SEU Tolerant Memory Cell Derived From Fundamental Studies of SEU Mechanisms in SRAM
    • Dec.
    • H.T.Weaver et. al. “An SEU Tolerant Memory Cell Derived From Fundamental Studies of SEU Mechanisms in SRAM,” IEEE Transactions on Nuclear Science, Vol. NS34, No. 6, pp. 1281, Dec. 1987
    • (1987) IEEE Transactions on Nuclear Science , vol.NS34 , Issue.6 , pp. 1281
    • Weaver, H.T.1
  • 10
    • 0022911819 scopus 로고
    • An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMs
    • Dec.
    • R.L.Johnson, Jr. and S.E.Diehl, “An Improved Single Event Resistive-Hardening Technique for CMOS Static RAMs,” IEEE Transactions of Nuclear Science, Vol. NS33, No. 6, pp. 1730, Dec.1986
    • (1986) IEEE Transactions of Nuclear Science , vol.NS33 , Issue.6 , pp. 1730
    • Johnson, R.L.1    Diehl, S.E.2
  • 11
    • 0022246886 scopus 로고
    • Single Event Upset Immune Integrated Circuits for Project Galileo
    • Dec.
    • A.E.Giddings, “Single Event Upset Immune Integrated Circuits for Project Galileo,” IEEE Transactions of Nuclear Science, Vol. NS32, No. 6, pp. 4159, Dec.1985
    • (1985) IEEE Transactions of Nuclear Science , vol.NS32 , Issue.6 , pp. 4159
    • Giddings, A.E.1
  • 12
    • 0026930097 scopus 로고
    • Simulated SEU Hardened Scaled CMOS SRAM Cell Design Using Gated Resistors
    • Oct.
    • L.R.Rockett, “Simulated SEU Hardened Scaled CMOS SRAM Cell Design Using Gated Resistors,” IEEE Transactions of Nuclear Science, Vol.39, No.5, 1532, Oct. 1992
    • (1992) IEEE Transactions of Nuclear Science , vol.39 , Issue.5
    • Rockett, L.R.1
  • 13
    • 84939722576 scopus 로고
    • Random Access Memory Immune to Single Event Upset Using a T-Resistor
    • US Patent No. 4809226, Feb.
    • Ochoa, Jr., “Random Access Memory Immune to Single Event Upset Using a T-Resistor,” US Patent No. 4809226, Feb.1989
    • (1989)
    • Ochoa, O.1
  • 14
    • 8444233093 scopus 로고
    • Circuit Reliability of Memory Cells with SEU Protection
    • Dec.
    • J.E.Vinson, “Circuit Reliability of Memory Cells with SEU Protection,” IEEE Transactions of Nuclear Science, Vol. NS39, No. 6, pp. 1671, Dec.1992
    • (1992) IEEE Transactions of Nuclear Science , vol.NS39 , Issue.6 , pp. 1671
    • Vinson, J.E.1
  • 15
    • 84939732208 scopus 로고
    • Adapting Commercial Electronics to the Naturally Occurring Radiation Environment
    • N.Haddad and T.Scott, “Adapting Commercial Electronics to the Naturally Occurring Radiation Environment,” IEEE NSREC Short Course, 1994
    • (1994) IEEE NSREC Short Course
    • Haddad, N.1    Scott, T.2
  • 16
    • 0023454333 scopus 로고
    • A Proposed New Structure for SEU Immunity in SRAM Employing Drain Resistance
    • Nov.
    • A.Ochoa, Jr., C.L.Axness, H.T.Weaver, “A Proposed New Structure for SEU Immunity in SRAM Employing Drain Resistance,” IEEE Electron Device Letters, Vol. EDL-8, No. 11, pp. 537, Nov. 1987
    • (1987) IEEE Electron Device Letters , vol.EDL-8 , Issue.11 , pp. 537
    • Ochoa, A.1    Axness, C.L.2    Weaver, H.T.3
  • 17
    • 84939761819 scopus 로고
    • High Impedance-Coupled CMOS SRAM for Improved Single Event Immunity
    • U.S. Patent No. 4,805,148, Feb.
    • S.E.Diehl-Nagle and J.R.Hauser, “High Impedance-Coupled CMOS SRAM for Improved Single Event Immunity,” U.S. Patent No. 4,805,148, Feb.1989
    • (1989)
    • Diehl-Nagle, S.E.1    Hauser, J.R.2
  • 18
    • 0024104188 scopus 로고
    • The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches
    • Nov.
    • S.E.Kerns, B.D.Shafer, “The Design of Radiation-Hardened ICs for Space: A Compendium of Approaches,” Proceedings of the IEEE, Vol. 76, No. 11, pp. 1470, Nov. 1988.
    • (1988) Proceedings of the IEEE , vol.76 , Issue.11 , pp. 1470
    • Kerns, S.E.1    Shafer, B.D.2
  • 19
    • 0024610684 scopus 로고
    • Twisted BitLine Architectures for Multi-Megabit Megabit DRAM's
    • Feb.
    • H.Hidaka et. al. “Twisted BitLine Architectures for Multi-Megabit Megabit DRAM’s,” IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, Feb., 1989
    • (1989) IEEE Journal of Solid-State Circuits , vol.24 , Issue.1
    • Hidaka, H.1
  • 20
    • 77957240968 scopus 로고
    • Static RAM with Single Event Immunity
    • European Patent Publication No. 0 342 466 A2, 23rd Nov.
    • F.Smith “Static RAM with Single Event Immunity,” European Patent Publication No. 0 342 466 A2, 23rd Nov. 1989
    • (1989)
    • Smith, F.1
  • 21
    • 0021476780 scopus 로고
    • Half-Vdd BitLine Sensing Scheme in CMOS DRAM's
    • Aug.
    • N.C.C.Lu and H.H.Chao, “Half-Vdd BitLine Sensing Scheme in CMOS DRAM’s,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 4, Aug., 1984
    • (1984) IEEE Journal of Solid-State Circuits , vol.SC-19 , Issue.4
    • Lu, N.C.C.1    Chao, H.H.2
  • 23
    • 0023562594 scopus 로고
    • Single-Event Upset (SEU) in a DRAM with On-chip Error Correction
    • Dec.
    • J.A.Zoutendyk et. al., “Single-Event Upset (SEU) in a DRAM with On-chip Error Correction,” IEEE Transactions of Nuclear Science, Vol. NS34, No.6, pp. 1310, Dec. 1987
    • (1987) IEEE Transactions of Nuclear Science , vol.NS34 , Issue.6 , pp. 1310
    • Zoutendyk, J.A.1
  • 24
    • 0026953435 scopus 로고
    • An On-Chip ECC Circuit for Correcting Soft Errors in DRAM's with Trench Capacitors
    • Nov.
    • P.Mazumder, “An On-Chip ECC Circuit for Correcting Soft Errors in DRAM's with Trench Capacitors,” IEEE Journal of Solid-State Circuits, Vol. 27, No. 11, pp.1623, Nov. 1992
    • (1992) IEEE Journal of Solid-State Circuits , vol.27 , Issue.11 , pp. 1623
    • Mazumder, P.1
  • 25
    • 0021506513 scopus 로고
    • A 288K CMOS Pseudostatic RAM
    • Oct.
    • H.Kawamoto et. al. “A 288K CMOS Pseudostatic RAM,” IEEE Journal of Solid-State Circuits, Vol. SC-19, No. 5, pp 619, Oct. 1984
    • (1984) IEEE Journal of Solid-State Circuits , vol.SC-19 , Issue.5 , pp. 619
    • Kawamoto, H.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.