Single-chip RSA processor implemented in a 0.5 μm rule gate array

Proceedings of the Annual IEEE International ASIC Conference and Exhibit

Volumn , Issue , 1994, Pages 433-436

  Ishii, Shinji ^a   Ohyama, Katsuichi ^a   Yamanaka, Kiyoshi ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CRYPTOGRAPHY; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; LSI CIRCUITS; PERFORMANCE; TELECOMMUNICATION SYSTEMS;

OPERATIONAL FUNCTIONS; PUBLIC KEY ENCRYPTION ALGORITHM; RULE GATE ARRAY;

MICROPROCESSOR CHIPS;

EID: 0028697063     PISSN: 10630988     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)