Automated multi-cycle symbolic timing verification of microprocessor-based designs

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 113-119

  Gupta, Anurag P ^a   Siewiorek, Daniel P ^a  

^a CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

AUTOMATION; COMPUTER CIRCUITS; COMPUTER SIMULATION; CONSTRAINT THEORY; GRAPH THEORY; LOGIC CIRCUITS; LOGIC DESIGN; MICROPROCESSOR CHIPS;

CENTRAL PROCESSING UNIT; COMBINATIONAL PATH TRACING; MICROPROCESSOR BASED DESIGNS; MULTI CYCLE SYMBOLIC TIMING VERIFICATION; SEQUENTIAL PATH TRACING; STATE TRANSITION GRAPH;

TIMING CIRCUITS;

EID: 0028599642     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196299     Document Type: Conference Paper

References (16)