Analysis of timing jitter in CMOS ring oscillators

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1994, Pages 27-30

  Weigandt, Todd C ^a   Kim, Beomsup ^a   Gray, Paul R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; DESIGN; ELECTRIC INVERTERS; ELECTRIC POWER SUPPLIES TO APPARATUS; ERRORS; MATHEMATICAL MODELS; MONTE CARLO METHODS; THERMAL NOISE; TIMING CIRCUITS; TRANSISTORS; WAVEFORM ANALYSIS;

BIAS VOLTAGE; CMOS RING OSCILLATOR; PHASE NOISE; POWER CONSUMPTION; SOURCE COUPLED DIFFERENTIAL RESISTIVELY LOADED DELAY CELLS; TIMING ERROR; TIMING JITTER;

OSCILLATORS (ELECTRONIC);

EID: 0028599627     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)