Rectification of multiple logic design errors in multiple output circuits

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 212-217

  Tomita, Masahiro ^a   Yamamoto, Tamotsu ^a   Sumikawa, Fuminori ^a   Hirano, Kotaro ^a  

^a KOBE UNIVERSITY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN FUNCTIONS; CODING ERRORS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DATA HANDLING; DECISION TABLES; LOGIC GATES; MATHEMATICAL MODELS; SIGNAL FILTERING AND PREDICTION;

BENCHMARK CIRCUITS; BINARY DECISION DIAGRAMS; ERROR POSSIBILITY INDEX; LOGIC DIAGNOSIS; MULTIPLE LOGIC DESIGN ERRORS; SIX VALUED SIMULATION METHOD;

COMPUTER AIDED LOGIC DESIGN;

EID: 0028594649     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196356     Document Type: Conference Paper

References (19)