High performance CMOS macromodule layout synthesis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1994, Pages 179-182

  Kim, Jaewon ^a   Kang, S M ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; COMPUTATIONAL COMPLEXITY; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL PROGRAMMING; MICROPROCESSOR CHIPS; TERMINOLOGY; USER INTERFACES;

CHANNELLESS ROUTING; CIRCUIT DELAYS; CONVEX PROGRAMMING TECHNIQUES; FLEXIBLE LOGIC CELL ARRAY PLATFORM; MACROMODULES;

CMOS INTEGRATED CIRCUITS;

EID: 0028573753     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (8)