Efficient and robust test generation-based timing analysis

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1994, Pages 303-306

  Marques Silva, Joao P ^a   Sakallah, Karem A ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMBINATORIAL CIRCUITS; HEURISTIC METHODS; LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; PERTURBATION TECHNIQUES; SENSITIVITY ANALYSIS;

CONCURRENT PATH SENSITIZATION; FLOATING MODE SENSITIZATION; GATE LEVEL COMBINATORIAL CIRCUIT; PATH SENSITIZATION MODEL; SEARCH SPACE PRUNING TECHNIQUE; SIGNAL PROPAGATION DELAY; TEST PATTERN GENERATION;

TIMING CIRCUITS;

EID: 0028572680     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (11)