Dual (n+/p+) polycide gate technology using Si-rich WSix to exterminate lateral dopant diffusion

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1994, Pages 117-118

  Fujii, Toyokazu ^a   Hashimoto, Shin ^a   Hori, Takashi ^a  

^a PANASONIC CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; CMOS INTEGRATED CIRCUITS; COMPOSITION EFFECTS; DIFFUSION; GRAIN GROWTH; ION IMPLANTATION; PHASE TRANSITIONS; SEMICONDUCTING SILICON; SILICON ON INSULATOR TECHNOLOGY; TUNGSTEN COMPOUNDS; X RAY ANALYSIS;

DOPANT; DUAL POLYCIDE GATE TECHNOLOGY; THRESHOLD VOLTAGE SHIFT; TUNGSTEN SILICIDE; X RAY DIFFRACTION;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0028571335     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)