Synthesis of instruction sets for pipelined microprocessors

Proceedings - Design Automation Conference

Volumn , Issue , 1994, Pages 5-11

  Huang, Ing Jer ^a   Despain, Alvin M ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BINARY SEQUENCES; CODES (SYMBOLS); COMPUTATIONAL LINGUISTICS; COMPUTER HARDWARE; CONSTRAINT THEORY; DATA STORAGE EQUIPMENT; PIPELINE PROCESSING SYSTEMS; SCHEDULING; SIMULATION; SYSTEMS ANALYSIS; USER INTERFACES;

ASSEMBLY CODE; BINARY TUPLE; INSTRUCTION SETS; MICROOPERATIONS; PIPELINED MICROPROCESSORS; SIMULATED ANNEALING SCHEME;

COMPUTER OPERATING PROCEDURES;

EID: 0028570708     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/196244.196250     Document Type: Conference Paper

References (14)