Reduction of wiring capacitance with new low dielectric SiOF interlayer film for high speed/low power sub-half micron CMOS

Digest of Technical Papers - Symposium on VLSI Technology

Volumn , Issue , 1994, Pages 59-60

  Ida, J ^a   Yoshimaru, M ^a   Usami, T ^a   Ohtomo, A ^a   Shimokawa, K ^a   Kita, A ^a   Ino, M ^a  

^a OKI ELECTRIC INDUSTRY CO   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; DELAY CIRCUITS; DIELECTRIC FILMS; ELECTRIC PROPERTIES; MOSFET DEVICES; NAND CIRCUITS; PERFORMANCE; SILICON COMPOUNDS;

CAPACITANCE REDUCTION; GAP FILLING PROPERTY; SCALING; SILICON OXIDE;

CMOS INTEGRATED CIRCUITS;

EID: 0028565181     PISSN: 07431562     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)