Extremely low-power bipolar current-mode I/O circuit for multi-Gbit/s interfaces

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1994, Pages 31-32

  Kawamura, Tomoaki ^a   Suzuki, Masao ^a   Ichino, Haruhiko ^a  

^a NTT CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC LOSSES; ELECTRIC NETWORK ANALYSIS; EMITTER COUPLED LOGIC CIRCUITS; IMPEDANCE MATCHING (ELECTRIC); INTERFACES (COMPUTER); SIGNAL TO NOISE RATIO;

LOW POWER BIPOLAR CURRENT MODE I/O CIRCUIT; NOISE IMMUNITY;

BIPOLAR INTEGRATED CIRCUITS;

EID: 0028564364     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (1)