Area-time analysis of carry lookahead adders using enhanced multiple output domino logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 4, Issue , 1994, Pages 59-62

  Wang, June ^a   Wang, Zhongde ^a   Jullien, G A ^a   Miller, W C ^a  

^a UNIVERSITY OF WINDSOR   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CASCADE CONNECTIONS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DIGITAL ARITHMETIC; LOGIC GATES; MATHEMATICAL OPERATORS; TECHNOLOGY; TRANSISTORS;

CARRY LOOKAHEAD ADDERS; ENHANCED MULTIPLE OUTPUT DOMINO LOGIC; GATE FAN IN; INTEGRATED CIRCUIT SYNTHESIS;

ADDERS;

EID: 0028561634     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)