15-150 MHz, all-digital phase-locked loop with 50-cycle lock time for high-performance low-power microprocessors

IEEE Symposium on VLSI Circuits, Digest of Technical Papers

Volumn , Issue , 1994, Pages 35-36

  Lundberg, Jim ^a   Nuckolls, Ed ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DIGITAL ARITHMETIC; DIGITAL CIRCUITS; DIGITAL CONTROL SYSTEMS; ENERGY UTILIZATION; GAIN CONTROL; PHASE LOCKED LOOPS; STABILITY; VARIABLE FREQUENCY OSCILLATORS;

ALL DIGITAL PHASE LOCKED LOOP; HIGH PERFORMANCE LOW POWER MICROPROCESSOR;

MICROPROCESSOR CHIPS;

EID: 0028555912     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)