Impact of Distributed Gate Resistance on the Performance of MOS Devices

IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

Volumn 41, Issue 11, 1994, Pages 750-754

  Razavi, Behzad ^a   Yan, Ran Hong ^a   Lee, Kwing F ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT OSCILLATIONS; ELECTRIC RESISTANCE; FREQUENCY RESPONSE; GATES (TRANSISTOR); LUMPED PARAMETER NETWORKS; PERFORMANCE; THERMAL NOISE;

CUT OFF FREQUENCY; DISTRIBUTED GATE RESISTANCE; NEGATIVE METAL OXIDE SEMICONDUCTOR (NMOS) TRANSISTORS; OSCILLATION MAXIMUM FREQUENCY; RESPONSE TIME;

MOS DEVICES;

EID: 0028547702     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.331530     Document Type: Article

References (7)

1. R. H. Yan et al., “89-GHz fT room-temperature silicon MOSFETs” IEEE Electron. Device Lett., vol. 13, pp. 256–258, May 1992.
2. K. F. Lee et al, “Room temperature 0.1-µm CMOS technology with 11.8 psec gate delay,” IEDM Tech. Dig., pp. 131–134, Dec. 1993.
3. R. H. Yan, unpublished results.
4. E. S. Kuh and R. A. Rohrer, Theory of Linear Active Networks. San Francisco, CA: Holden-Day Inc., 1967.
5. P. Wolf, “Microwave properties of Schottky-barrier field-effect transistors,” IBM J. Res. Develop., pp. 125–141, Mar. 1970.
6. S. Ohkawa et al., “Low noise GaAs field-effect transistors,” Fujitsu Scient. Tech. J., pp. 151–173, Mar. 1975.
7. I. Bahl and P. Bhartia, Microwave Solid State Circuit Design. New York: John Wiley & Sons, 1988.