Effect of Low and High Temperature Anneal on Process-Induced Damage of Gate Oxide

IEEE Electron Device Letters

Volumn 15, Issue 11, 1994, Pages 475-476

  King, Joseph C ^a   Hu, Chenming ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING; ELECTRIC BREAKDOWN; ELECTRIC CHARGE; HIGH TEMPERATURE EFFECTS; INTERFACES (MATERIALS); ION IMPLANTATION; LOW TEMPERATURE EFFECTS; OXIDES; PLASMA ETCHING; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR DEVICE STRUCTURES;

ELECTRICAL STRESS; GATE OXIDE; INTERFACE TRAP GENERATION; OXIDE CHARGE TRAPPING; PROCESS INDUCED DAMAGE; WAFER CHARGING;

GATES (TRANSISTOR);

EID: 0028544536     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.334672     Document Type: Article

References (8)

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