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Volumn 29, Issue 11, 1994, Pages 1323-1329

An SOI-DRAM with Wide Operating Voltage Range by CMOS/SIMOX Technology

Author keywords

[No Author keywords available]

Indexed keywords

CELLULAR ARRAYS; CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR STORAGE; SILICON ON INSULATOR TECHNOLOGY; SUBSTRATES; THICK FILMS;

EID: 0028542559     PISSN: 00189200     EISSN: 1558173X     Source Type: Journal    
DOI: 10.1109/4.328631     Document Type: Article
Times cited : (28)

References (9)
  • 1
    • 85051940193 scopus 로고
    • Future technological and economic prospects for VLSI
    • H. Komiya, “Future technological and economic prospects for VLSI,” ISSCC Dig. Tech. Papers, pp. 16-19, 1993.
    • (1993) ISSCC Dig. Tech. Papers , pp. 16-19
    • Komiya, H.1
  • 2
    • 30244511119 scopus 로고
    • A new stacked cell structure for Giga-bit DRAM’s using vertical ultra-thin SOI (DELTA) MOSFETs
    • D. Hisamoto et al., “A new stacked cell structure for Giga-bit DRAM’s using vertical ultra-thin SOI (DELTA) MOSFETs,” IEDM Tech. Dig., pp. 959-961, 1991.
    • (1991) IEDM Tech. Dig. , pp. 959-961
    • Hisamoto, D.1
  • 3
    • 84975345286 scopus 로고
    • A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAM’s
    • T. Nishihara et al., “A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAM’s IEDM Tech. Dig., pp. 803-806, 1992.
    • (1992) IEDM Tech. Dig. , pp. 803-806
    • Nishihara, T.1
  • 4
    • 0023604289 scopus 로고
    • Soft error rate of 64 K SOI-DRAM
    • H. Gotou et al., “Soft error rate of 64 K SOI-DRAM,” IEDM Tech. 1987.
    • (1987) IEDM Tech.
    • Gotou, H.1
  • 5
    • 0028124010 scopus 로고
    • An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology
    • K. Suma et al., “An SOI-DRAM with wide operating voltage range by CMOS/SIMOX technology,” ISSCC Dig. Tech. Papers, pp. 138-139, 1994.
    • (1994) ISSCC Dig. Tech. Papers , pp. 138-139
    • Suma, K.1
  • 7
    • 0027876188 scopus 로고
    • A well-synchronized sensing/equalizing method for sub-l.OV operating advanced DRAM’s
    • T. Ooishi et al., “A well-synchronized sensing/equalizing method for sub-l.OV operating advanced DRAM’s,” 1993 Symp. on VLSI Circuits Tech. 81-82.
    • (1993) Symp. on VLSI Circuits Tech. , pp. 81-82
    • Ooishi, T.1
  • 8
    • 0027845427 scopus 로고
    • ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation
    • T. Eimori et al., “ULSI DRAM/SIMOX with stacked capacitor cells for low-voltage operation,” IEDM Tech. Dig., pp. 45-47, 1993.
    • (1993) IEDM Tech. Dig. , pp. 45-47
    • Eimori, T.1
  • 9
    • 0023456714 scopus 로고
    • Mechanism of bit line mode soft error for DRAM
    • M. Asakura et al., “Mechanism of bit line mode soft error for DRAM,” Trans. IEICE, vol. 70, no. 11, pp. 1060-1061, 1987.
    • (1987) Trans. IEICE , vol.70 , Issue.11 , pp. 1060-1061
    • Asakura, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.