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Journal of VLSI Signal Processing

Volumn 8, Issue 2, 1994, Pages 169-181

High-speed VLSI architectures for soft-output viterbi decoding

(3) Joeressen, Olaf J a Vaupel, Martin a Meyr, Heinrich a

a RWTH AACHEN UNIVERSITY (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTATIONAL COMPLEXITY; DECODING; STORAGE ALLOCATION (COMPUTER);

CONCATENATED SYSTEMS; IMPLEMENTATION EFFICIENCY; SOFT OUTPUT VITERBI-ALGORITHM; STORAGE REQUIREMENTS;

VLSI CIRCUITS;

EID: 0028530119 PISSN: 09225773 EISSN: 1573109X Source Type: Journal
DOI: 10.1007/BF02109383 Document Type: Article

Times cited : (8)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.