Automated Synthesis of PseudoExhaustive Test Generator in VLSI BIST Design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 3, 1994, Pages 273-291

  Chen, Chien In Henry ^a   Yuen, Joel T ^a  

^a WRIGHT STATE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BUILT IN SELF TEST; PSEUDO-EXHAUSTIVE TEST GENERATOR; VLSI DESIGN;

COMPUTATIONAL COMPLEXITY; COMPUTER HARDWARE; COMPUTER SIMULATION; COMPUTER SYSTEMS; CONTROLLABILITY; ELECTRIC NETWORK ANALYZERS; MICROPROCESSOR CHIPS; OBSERVABILITY; TRANSISTORS; VLSI CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER AIDED DESIGN; COMPUTER AIDED NETWORK ANALYSIS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING;

INTEGRATED CIRCUIT TESTING; VLSI CIRCUITS;

BUILD IN SELF TEST (BIST) DESIGN; SOFTWARE PACKAGE BISTSYN; THREE PHASE CLUSTER PARTITIONING;

EID: 0028501887     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.311637     Document Type: Article

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