Logic Design Error Diagnosis and Correction

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 2, Issue 3, 1994, Pages 320-332

  Chung, Pi Yu ^a   Hajj, Ibrahim N ^b  

^a LUCENT TECHNOLOGIES   (United States)

^b UNIVERSITY OF ILLINOIS AT URBANA CHAMPAIGN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; BOOLEAN ALGEBRA; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ERROR CORRECTION; ERROR DETECTION; INTEGRATED CIRCUIT LAYOUT; LOGIC DESIGN; LOGIC GATES; SET THEORY; BOOLEAN FUNCTIONS; COMPUTER AIDED SOFTWARE ENGINEERING; COMPUTER HARDWARE DESCRIPTION LANGUAGES; DIGITAL COMPUTERS; ERROR ANALYSIS; ERROR COMPENSATION; FORMAL LANGUAGES; LOGIC CIRCUITS;

GATE CORRECTION; LOGIC VERIFICATION TOOLS;

DIGITAL INTEGRATED CIRCUITS; LOGIC DESIGN;

BOOLEAN EQUATION; DESIGN ERRORS; DIGITAL SYSTEM; ERROR DIAGNOSIS; LOGIC VERIFICATION TOOLS;

EID: 0028501880     PISSN: 10638210     EISSN: 15579999     Source Type: Journal    
DOI: 10.1109/92.311641     Document Type: Article

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