Capacitance Calculation of IC Packages Using the Finite Element Method and Planes of Symmetry

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 9, 1994, Pages 1159-1166

  Chou, Tai Yu ^a   Cendes, Zoltan J ^b  

^a AGERE SYSTEMS   (United States)

^b CARNEGIE MELLON UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CALCULATIONS; CAPACITANCE; COMPUTER SIMULATION; ELECTRIC CONDUCTORS; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; MATHEMATICAL MODELS; MATRIX ALGEBRA; THREE DIMENSIONAL; VECTORS;

CAPACITANCE CALCULATIONS; DUAL IN LINE PACKAGE; INTEGRATED CIRCUITS PACKAGES; INTERCONNECTION STRUCTURES; PLANES OF SYMMETRY; PLASTIC LEADED CHIP CARRIER;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0028500641     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.310904     Document Type: Article

References (10)

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