A Method for Pseudo Exhaustive Test Pattern Generation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 9, 1994, Pages 1170-1178

  Kagaris, Dimitrios ^a   Makedon, Fillia ^a   Tragoudas, Spyros ^b  

^a DARTMOUTH COLLEGE   (United States)

^b SOUTHERN ILLINOIS UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

GRAPH THEORY; LOGIC GATES; MATHEMATICAL MODELS; SHIFT REGISTERS;

BYPASS STORAGE CELLS; CIRCUIT UNDER TEST; LINEAR FEEDBACK SHIFT REGISTERS; PSEUDO EXHAUSTIVE TEST PATTERN GENERATION;

INTEGRATED CIRCUIT TESTING;

EID: 0028500250     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.310906     Document Type: Article

References (23)

1. M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design. New York: Computer Science Press, 1990.
2. P. H. Bardell, W. H. McAnney, and J. Savir, Built-in Test for VLSI. New York: Wiley, 1987.
3. Z. Barzilai, D. Coppersmith, and A. L. Rosenberg, “Exhaustive Bit Generation with Application to VLSI Self-Testing.” IEEE Trans. Comput. vol. 32, pp. 190–194, Feb. 1983.
4. E. R. Berlekamp, Algebraic Coding Theory. Laguna Hills, CA: Aegean Park Press, 1984.
5. S. N. Bhatt, F. R. K. Chung, and A. L. Rosenberg, “Partitioning Circuits for Improved Testability, ” Algorithmica, no. 6, pp. 37-48, 1991.
6. F. Brglez, P. Pownall, and R. Hum, “Accelerated ATPG and Fault Grading via Testability Analysis,” in Proc. IEEE Int. Symp. on Circuits and Systems, 1985, pp. 695–698.
7. T. H. Cormen, C. E. Leiserson, and R. L. Rivest, Introduction to Algorithms. Cambridge, MA: MIT Press, 1990.
8. S.W. Golomb, Shift Resister Sequences. Laguna Hills, CA: Aegean Park Press, 1982.
9. J.J. Hallenbeck, J.R. Cybrynski, N. Kanopoulos, T. Markas, and N. Vasanthavada, “The Test Engineer's Assistant: A Support Environment for Hardware Design for Testability,” Computer, vol. 22, pp. 59–68. Apr. 1989.
10. W.B. Jone and C. A. Papachristou, “A Coordinated Approach to Partitioning and Test Pattern Generation for Pseudoexhaustive Testing,” in Proc. 26th ACM/IEEE Design Automat. Conf., 1989, pp. 525 – 530.
11. D. Kagaris, F. Makedon, and S. Tragoudas, “On Minimizing Hardware Overhead for Pseudo Exhaustive Circuit Testability,” in Proc. IEEE Int. Conf. Computer Design, 1992, pp. 358–364.
12. D. Kagaris, “Automatic Test Pattern Generation Techniques for Built-In In Self-Test of Digital Circuits,” Ph.D. Thesis, Dartmouth College, Hanover, NH, 1994.
13. A. Lempel and M. Cohn, “Design of universal test sequences for VLSI,” IEEE Trans. Inform. Theory, vol. 31, pp. 10–15. Jan. 1985.
14. E. J. McCluskey and S. Bozorgui-Nesbat, “Design for Autonomous Test,” IEEE Trans. Comput., vol. 30, pp. 866–875, Nov. 1981.
15. E. J. McCluskey, “Verification Testing—A Pseudoexhaustive Test Technique,” IEEE Trans. Comput., vol. 33, pp. 541–546, June 1981.
16. E. J. McCluskey, “Built-in Self-Testing Techniques,” IEEE Design and Test, pp. 21–28, Apr. 1985.
17. A. Mennone and R. L. Russo, “An Example Computer Graph and Its Partitions and Mappings,” IEEE Trans. Camput’., vol. 23, pp. 1198–1204, 1974.
18. W. W. Peterson and E. J. Weldon, Error-Correcting Codes. Cambridge, MA: MIT Press, 1972.
19. M. W. Roberts and M. S. Lala, “An Algorithm for the Partitioning of Logic Circuits,” IEE Proc., vol. 131, Pt. E, no. 4, pp. 113-118, 1984.
20. D. T. Tang and C. L. Chen, “Logic test pattern generation using linear codes,” IEEE Trans. Camput., vol. 33, pp. 845–850, June 1984.
21. Texas Instruments Inc. Eng. Staff, The TTL Data Book for Design Engineers, 2nd ed., Texas Instruments Inc., 1976.
22. J. G. Udell, Jr., “Test Set Generation for Pseudoexhaustive BIST,” in Proc. Int. Conf. Computer-Aided Design, 1986, pp. 52–55.
23. H. Wunderlich and S. Hellebrand, “The Pseudoexhaustive Test of Sequential Circuits,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 26–32, Jan. 1992.