Reference Plane Parasitics Modeling and Their Contribution to the Power and Ground Path “Effective” Inductance as Seen by the Output Drivers

IEEE Transactions on Microwave Theory and Techniques

Volumn 42, Issue 9, 1994, Pages 1765-1773

  Senthinathan, Ramesh ^a   Cangellaris, Andreas C ^b   Prince, John L ^b  

^a MOTOROLA INC   (United States)

^b Department of Electrical ^*  (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK PARAMETERS; ELECTRONICS PACKAGING; EQUIVALENT CIRCUITS; MATHEMATICAL MODELS; OPTIMIZATION; PARAMETER ESTIMATION; SPURIOUS SIGNAL NOISE;

CHIP PACKAGE INTERFACE; GROUND PATH EFFECTIVE INDUCTANCE; OUTPUT DRIVERS; POWER EFFECTIVE INDUCTANCE; REFERENCE PLANE PARASITICS; SIMULTANEOUS SWITCHING NOISE;

ELECTRIC CURRENT DISTRIBUTION;

EID: 0028499553     PISSN: 00189480     EISSN: 15579670     Source Type: Journal    
DOI: 10.1109/22.310586     Document Type: Article

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