1-Mb Memory Chip Using Giant Magnetoresistive Memory Cells

IEEE Transactions on Components Packaging and Manufacturing Technology Part A

Volumn 17, Issue 3, 1994, Pages 373-379

  Brown, J L ^a   Pohm, A V ^a  

^a NVE CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COPPER ALLOYS; ELECTRIC POWER SUPPLIES TO APPARATUS; ELECTRIC RESISTANCE; GATES (TRANSISTOR); INTEGRATED CIRCUIT LAYOUT; MAGNETIC MATERIALS; MAGNETIZATION; MICROPROCESSOR CHIPS; RANDOM ACCESS STORAGE; READOUT SYSTEMS; REDUNDANCY;

ARRAY AREA; GATE LENGTHS; GIANT MAGNETORESISTANCE RATIO; MAGNETORESISTIVE MEMORY CELLS; MEMORY CHIP; READ ACCESS TIME;

CELLULAR ARRAYS;

EID: 0028496774     PISSN: 10709886     EISSN: None     Source Type: Journal    
DOI: 10.1109/95.311746     Document Type: Article

References (7)

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2. H.Y. Yoo, A.V. Pohm, J.H. Hur, S.W. Kenkare, and C.S. Comstock, “Dynamic switching process of sandwich-structured MR elements,” IEEE Trans. Magn., vol. 25, pp. 4269–71, Sept. 1989.
3. A.V. Pohm, C.S. Comstock, J.M. Daughton, and D.R. Krahn, “Ultra high density non destructive read out MR memory cells,” in Proc. Comp. Euro, pp. 1-24–26, May 1989.
4. A.V. Pohm, J.S.T. Huang, J.M. Daughton, D.R. Krahn, and V. Mehra, “The design of a one megabit nonvolatile M-R memory chip using 1.5 x 5 cells,” IEEE Trans. Magn., vol. 28, pp. 3117–3119, Nov. 1988.
5. J.M. Daughton, “Magnetoresistive memory technology,” Thin Solid Films, vol. 216, pp. 162–168, 1992.
6. R.L. Wiker, “High density MRM memory technology in advanced signal, data, control processors and other memory systems,” in Proc. Nonvolatile Memory Technology Review, 1993, pp. 38–42.
7. M.N. Baibich, J.M. Broto, A. Fert, F. Nguyen Van Dau, and F. Petroff, “Giant magnetoresistance of 001 Fe/000 Cr magnetic sublattices,” Phys. Rev. Lett., vol. 61, pp. 21, 1988.