A Parallel-In-Time Method for the Transient Simulation of SOI Devices With Drain Current Overshoots

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 13, Issue 8, 1994, Pages 1035-1044

  Tai, Gwo Chung ^a   Korman, Can E ^b   Mayergoyz, Isaak D ^c  

^a Meta Software Inc   (United States)

^b GEORGE WASHINGTON UNIVERSITY   (United States)

^c UNIVERSITY OF MARYLAND   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; COMPUTER SIMULATION; FINITE DIFFERENCE METHOD; FORTRAN (PROGRAMMING LANGUAGE); ITERATIVE METHODS; PARALLEL PROCESSING SYSTEMS; RESPONSE TIME (COMPUTER SYSTEMS); SEMICONDUCTOR DEVICES; SILICON ON INSULATOR TECHNOLOGY; TIME DOMAIN ANALYSIS; TRANSIENTS;

CPU TIME; DRAIN CURRENT OVERSHOOTS; PARALLEL IN TIME METHOD; SOI DEVICES; TRANSIENT SIMULATION;

SEMICONDUCTOR DEVICE MODELS;

EID: 0028484779     PISSN: 02780070     EISSN: 19374151     Source Type: Journal    
DOI: 10.1109/43.298039     Document Type: Article

References (27)

1. K.C. Wu and R. W. Dutton, “Parallel solutions of mega-scale 3D device simulations,” in Proc. Int. Workshop on Computational Electronics, May 28–29, 1992, Univ. of Illinois at Urbana-Champaign, pp. 99–102.
2. D. M. Webber, E. Tomacruz, R. Guerrieri, T. Toyabe, and A. Sangiovanni-Vincentelli, “A massively parallel algorithm for three-dimensional dimensional device simulation,” IEEE Trans. Computer-Aided Design, vol. 10, 1201–1209, Sept. 1991.
3. C. Gardnar, P. J. Lanzkron, and D. J. Rose, “A parallel block iterative method for the hydrodynamic device model,” IEEE Trans. Computer-Aided Aided Design, vol. 10, pp. 1187–1192, Sept. 1991.
4. J. P. Darling and I. D. Mayergoyz, “Data parallel algorithm for the numerical modeling of semiconductor devices,” Data Parallel Research Initiative (DPRI) Symp. Dig. DEC External Research Program. Symp. Dig., DEC External Research Program, Maynard MA, June 1992.
5. J. P. Darling and I. D. Mayergoyz, “Parallel algorithm for the solution of nonlinear Poisson equation of semiconductor theory and its implementation on the MPP” J. Parallel and Distributed Comput.,vol. 8, pp 161−168 1990.
6. P. F. Cox, R. G. Burch, D. E. Hocevar, P. Yang, and B. D. Epler, “Direct circuit simulation algorithms for parallel processing,” IEEE Trans. Computer-Aided Design, vol. 10, pp. 714–725, June 1991.
7. E. Z. Xia and R. A. Saleh, “Parallel waveform-newton algorithm for circuit simulation,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 432–442, 1992.
8. S. A. Kravitz, R. E. Bryant, and R. A. Rutenbar, “Massively parallel switch-level simulation: A feasibility study,” IEEE Trans Computer-Aided Aided Design, vol. 10, p. 871, July 1991.
9. N. Funabiki and Y. Takefuji, “A parallel algorithm for channel routing problem,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 464–474, Apr. 1992.
10. K. P. Belkhale and P. Banerjee, “Parallel algorithm for VLSI circuit extraction,” IEEE Trans. Computer-Aided Design, vol. 11, pp. 604–618, May 1991.
11. I. D. Mayergoyz, “Solution of the nonlinear Poisson equation of semi conductor device theory,” J. Appl. Phys., vol. 59, no. 1, pp. 195–199, Jan. 1986.
12. C. E. Korman and I. D. Mayergoyz, “A globally convergent algorithm for the solution of the steady-state semiconductor device equations,” J. Appl. Phys., vol. 68, no. 3, pp. 1324–1334, Aug. 1990.
13. M. Gaitan, I. D. Mayergoyz, and C. E. Korman, “Investigation of the threshold voltage of MOSFET's with position- and energy-dependent interface trap distributions using a fixed-point iteration method,” IEEE Trans. Electron Devices, vol. 37, pp. 1031–1038, Apr. 1990.
14. C. E. Korman, I. D. Mayergoyz, M. Gaitan, and G.C. Tai, “An efficient method to compute the maximum transient drain current overshoot in silicon on insulator devices,” J. Appl. Phys., vol. 73, no. 6, p. 2611, 1993.
15. G.C. Tai, J. Darling, and 1. D. Mayergoyz, “Fixed-point iteration technique for the transient simulation of semiconductor devices on massively parallel SIMD computers” in Proc. High Performance ComputingGrand Challenges in Compurer Simulation, Mar. 29-Apr. I, 1993, Arlington, VA, pp. 102-107.
16. G.C. Tai, J. Darling, and I. D. Mayergoyz, “A prediction-correction parallel-in-time transient simulation of SO1 MOSFETs” in Proc. Int. Devices and Materials Symp., 1992, Taipei, Taiwan, pp. 67-70.
17. M. Yoshimi, M. Takahashi, T. Wada, K. Tato, S. Kambayashi, M. Kemmochi, and K. Natori, “Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFET's,” IEEE Trans. Electron Devices, vol. 37, pp. 2015–2021, Sept. 1990.
18. A. Hiroki, S. Odanaka, K. Ohe, and H. Esaki, “A mobility model for sub-micrometer micrometer MOSFET simulation including hot-carrier-induced device degradation,” IEEE Trans. Electron Devices, vol. 35, pp. 1487–1493, Sept. 1988.
19. D. L. Scharfetter and H. K. Gummel, “Large-signal analysis of a silicon read diode oscillator,” IEEE Trans. Electron Devices, vol. 16, pp. 64–77, Jan. 1969.
20. T. I. Seidman and S. C. Choo, “Iterative scheme for the computer simulation of semiconductor devices,” Solid-State Electron., vol. 15, pp. 1229–1235, 1972.
21. K. Kato and K. Taniguchi, “Numerical analysis of switching characteristics in SOI MOSFET,” IEEE Trans. Electron Devices, vol. 33, pp. 133–139, Jan. 1986.
22. M. Yoshimi, H. Hazama, M. Takahashi, S. Kambayashi, T. Wada, K. Kato, and H. Tango, “Two-dimensional simulation and measurement of high performance MOSFET's made on a very thin SOI film,” IEEE Trans. Electron Devices, vol. 36, pp. 493–503, Mar. 1989.
23. R. L. Burden and J. D. Faires, Numerical Analysis, 4th Edition. Boston: PWS-KENT Publishing Co., 1989.
24. CM Fortran User's Guide Version 0.7-f, Thinking Machine Company, July 1990.
25. H. K. Lim and J. G. Fossum, “Transient drain current and propagation delay in SOI CMOS,” IEEE Trans. Electron Devices, vol. 31, pp. 1251–1258, Sept. 1984.
26. P. Wild, “On the stability of the time discretizations for the semiconductor equations,” COMPEL, vol. 10, no. 1, pp. 11–25, 1991.
27. R. F. Lucas, T. Blank, and J. J. Tiemann, “A parallel solution method for large sparse system” IEEE Trans. Computer-Aided Design, vol. 6, pp. 981-991, NOV.1987.