A Structured Testability Approach For Multichip Modules Based On Bist And Boundary-Scan

IEEE Transactions on Components Packaging and Manufacturing Technology Part B

Volumn 17, Issue 3, 1994, Pages 283-290

  Zorian, Yervant ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY; ELECTRONIC EQUIPMENT MANUFACTURE; ELECTRONIC EQUIPMENT TESTING; INTEGRATED CIRCUIT MANUFACTURE; NETWORK COMPONENTS; PERFORMANCE; PRINTED CIRCUIT BOARDS; PRODUCT DESIGN; QUALITY CONTROL; SEMICONDUCTING SILICON; SUBSTRATES; SURFACE MOUNT TECHNOLOGY;

BOUNDARY SCAN; BUILT IN SELF TEST; MULTICHIP MODULE TECHNOLOGY; TESTABILITY;

ELECTRONICS PACKAGING;

EID: 0028482847     PISSN: 10709894     EISSN: None     Source Type: Journal    
DOI: 10.1109/96.311775     Document Type: Article

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