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Volumn 17, Issue 9, 1994, Pages
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Interconnect challenge. Filling small, high aspect ratio contact holes
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NONE
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Author keywords
[No Author keywords available]
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Indexed keywords
CHEMICAL VAPOR DEPOSITION;
CMOS INTEGRATED CIRCUITS;
ELECTRIC CONTACTS;
SPUTTER DEPOSITION;
BARRIER/ADHESION LAYERS;
KEYHOLE VOID FORMATION;
RC DELAYS MINIMIZATION;
SIGNAL PROPAGATION DELAYS;
SILICIDES;
INTEGRATED CIRCUIT MANUFACTURE;
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EID: 0028480427
PISSN: 01633767
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
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Times cited : (4)
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References (0)
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