-
2
-
-
0025206726
-
Parallel Simulated Annealing Algorithms for Standard Cell Placement on Hypercube Multiprocessors
-
Jan.
-
P. Banerjee, M. H. Jones, and J. Sargent, “Parallel Simulated Annealing Algorithms for Standard Cell Placement on Hypercube Multiprocessors.” IEEE Trans. Parallel and Distributed Systems, no. 1, pp. 91–106, Jan. 1990.
-
(1990)
IEEE Trans. Parallel and Distributed Systems
, Issue.1
, pp. 91-106
-
-
Banerjee, P.1
Jones, M.H.2
Sargent, J.3
-
3
-
-
0024178326
-
PACE: A Parallel VLSI Circuit Extractor on the Intel Hypercube Multiprocessor
-
Nov.
-
K. P. Belkhale and P. Banerjee, “PACE: A Parallel VLSI Circuit Extractor on the Intel Hypercube Multiprocessor,” in Proc. Int. Conf. Computer Aided Design, Nov. 1988, pp. 326–329.
-
(1988)
Proc. Int. Conf. Computer Aided Design
, pp. 326-329
-
-
Belkhale, K.P.1
Banerjee, P.2
-
4
-
-
0024914714
-
PACE2: An Improved Parallel VLSI Extractor with Parameter Extraction
-
Nov.
-
K. P. Belkhale and P. Banerjee, “PACE2: An Improved Parallel VLSI Extractor with Parameter Extraction,” in Proc. Inc Conf. Computer Aided Design, Nov. 1989, pp. 526–530.
-
(1989)
Proc. Inc Conf. Computer Aided Design
, pp. 526-530
-
-
Belkhale, K.P.1
Banerjee, P.2
-
5
-
-
0026965951
-
A Portable Parallel Algorithm for Logic Synthesis Using Transduction
-
Nov.
-
K. De, B. Ramkumar, and P. Banerjee, “A Portable Parallel Algorithm for Logic Synthesis Using Transduction,” in Proc. Int. Conf Computer-Aided Aided Design, Nov. 1992, pp. 412–415.
-
(1992)
Proc. Int. Conf Computer-Aided Aided Design
, pp. 412-415
-
-
De, K.1
Ramkumar, B.2
Banerjee, P.3
-
6
-
-
25944480238
-
Supporting Machine Independent Programming on Diverse Parallel Architectures
-
Aug.
-
W. Fenton, B. Ramkumar, V. A. Saletore, A. B. Sinha, and L. V. Kale, “Supporting Machine Independent Programming on Diverse Parallel Architectures,” in Int. Conf Parallel Processing, Aug. 1990, pp. 193–201.
-
(1990)
Int. Conf Parallel Processing
, pp. 193-201
-
-
Fenton, W.1
Ramkumar, B.2
Saletore, V.A.3
Sinha, A.B.4
Kale, L.V.5
-
7
-
-
84911618187
-
MEXTRA: A Manhattan Circuit Extractor
-
University of California at Berkeley, Jan.
-
D. T. Fitzpatrick, “MEXTRA: A Manhattan Circuit Extractor,” Tech. Rep. Electronics Research Lab M82/42, University of California at Berkeley, Jan. 1982.
-
(1982)
Tech. Rep. Electronics Research Lab M82/42
-
-
Fitzpatrick, D.T.1
-
8
-
-
0020545820
-
ACE: A Circuit Extractor
-
June
-
A. Gupta, “ACE: A Circuit Extractor.” In Design Automation Conf, June 1983, pp. 721–725.
-
(1983)
Design Automation Conf
, pp. 721-725
-
-
Gupta, A.1
-
9
-
-
0022953206
-
Data Management and Graphics Editing in the Berkeley Design Environment
-
Nov.
-
D. S. Harrison, P. Moore, R. L. Spickelmier, and A. R. Newton, “Data Management and Graphics Editing in the Berkeley Design Environment,” in Proc. Int. Conf. Computer-Aided Design, Nov. 1986, pp. 24–27.
-
(1986)
Proc. Int. Conf. Computer-Aided Design
, pp. 24-27
-
-
Harrison, D.S.1
Moore, P.2
Spickelmier, R.L.3
Newton, A.R.4
-
12
-
-
0011678812
-
The Chare Kernel Parallel Programming System
-
Aug. August
-
L. V. Kale, “The Chare Kernel Parallel Programming System,” in list. Conf Parallel Processing, Aug. 1990, pp. 17–25, August 1990.
-
(1990)
list. Conf Parallel Processing
, pp. 17-25
-
-
Kale, L.V.1
-
13
-
-
0028101661
-
Prop-erPLACE: ErPLACE: A Portable Parallel Algorithm for Standard Cell Placement
-
Cancun, Mexico, Mar.
-
S. H. Kim, J. Chandy, S. Parkes, B. Ramkumar, and P. Banerjee, “Prop-erPLACE: ErPLACE: A Portable Parallel Algorithm for Standard Cell Placement.” In Proc. Int. Parallel Processing Symp., Cancun, Mexico, Mar. 1994.
-
(1994)
Proc. Int. Parallel Processing Symp
-
-
Kim, S.H.1
Chandy, J.2
Parkes, S.3
Ramkumar, B.4
Banerjee, P.5
-
15
-
-
84939358725
-
MACE: A Multiprocessor Approach to Circuit Extraction
-
Master's thesis, MIT, Cambridge, MA, June
-
S. Levitin, “MACE: A Multiprocessor Approach to Circuit Extraction,” Master's thesis, MIT, Cambridge, MA, June 1986.
-
(1986)
-
-
Levitin, S.1
-
16
-
-
84939723576
-
EXCL: A Circuit Extractor of IC Designs
-
June
-
S. P. McCormick, “EXCL: A Circuit Extractor of IC Designs,” in Design Automation Conf., June 1984, pp. 624–628.
-
(1984)
Design Automation Conf
, pp. 624-628
-
-
McCormick, S.P.1
-
18
-
-
0026175427
-
Parallel Test Generation for Sequential Circuits on General Purpose Multiprocessors
-
June
-
S. Patil, P. Banerjee, and J. H. Patel, “Parallel Test Generation for Sequential Circuits on General Purpose Multiprocessors,” in Proc. 28th Design Automation Conf, June 1991.
-
(1991)
Proc. 28th Design Automation Conf
-
-
Patil, S.1
Banerjee, P.2
Patel, J.H.3
-
19
-
-
0027005302
-
Portable Parallel Test Generation for Sequential Circuits
-
Nov.
-
B. Ramkumar and P. Banerjee, “Portable Parallel Test Generation for Sequential Circuits,” in Proc. Inc Conf. Computer-Aided Design, Nov. 1992, pp. 220–223.
-
(1992)
Proc. Inc Conf. Computer-Aided Design
, pp. 220-223
-
-
Ramkumar, B.1
Banerjee, P.2
-
21
-
-
0023978575
-
Parallel Cell Placement Algorithms with Quality Equivalent to Simulated Annealing
-
Mar.
-
J. S. Rose, W. M. Snelgrove, and Z. G. Vranesic, “Parallel Cell Placement Algorithms with Quality Equivalent to Simulated Annealing.” IEEE Trans. Computer-Aided Design, vol. 7, no. 3, pp. 387–396. Mar. 1988.
-
(1988)
IEEE Trans. Computer-Aided Design
, vol.7
, Issue.3
, pp. 387-396
-
-
Rose, J.S.1
Snelgrove, W.M.2
Vranesic, Z.G.3
-
23
-
-
0021404023
-
The TimberWolf Placement and Routing Package
-
C. Sechen and A. L. Sangiovanni-Vincentelli, “The TimberWolf Placement and Routing Package.” IEEE J. Solid-State Circuits, vol. 20, no. 2, pp. 510–522, 1988.
-
(1988)
IEEE J. Solid-State Circuits
, vol.20
, Issue.2
, pp. 510-522
-
-
Sechen, C.1
Sangiovanni-Vincentelli, A.L.2
-
25
-
-
0024628181
-
A Quadrisection-Based Combined Place and Route Scheme for Standard Cells
-
Mar.
-
P. Suaris and G. Kedem, “A Quadrisection-Based Combined Place and Route Scheme for Standard Cells,” IEEE Trans. Circuits and Systems, vol. 8, pp. 234–244, Mar. 1989.
-
(1989)
IEEE Trans. Circuits and Systems
, vol.8
, pp. 234-244
-
-
Suaris, P.1
Kedem, G.2
-
26
-
-
0025561401
-
Circuit Extraction on a Message Passing Multiprocessor
-
June
-
B. A. Tonkin, “Circuit Extraction on a Message Passing Multiprocessor,” in Design Automation Conf, June 1990, pp. 260–265.
-
(1990)
Design Automation Conf
, pp. 260-265
-
-
Tonkin, B.A.1
|