An All Implanted Self-Aligned Enhancement Mode n-JFET with Zn Gates for GaAs Digital Applications

IEEE Electron Device Letters

Volumn 15, Issue 7, 1994, Pages 242-244

  Sherwin, M E ^a   Zolper, J C ^a   Baca, A G ^a   Shul, R J ^a   Howard, A J ^a   Rieger, D J ^a   Klem, J F ^a   Hietala, V M ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC CURRENTS; GATES (TRANSISTOR); ION IMPLANTATION; LOGIC CIRCUITS; MICROWAVE MEASUREMENT; SEMICONDUCTING GALLIUM ARSENIDE; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE MANUFACTURE; SEMICONDUCTOR JUNCTIONS; TUNGSTEN; VOLTAGE MEASUREMENT; ZINC;

DRAIN IMPLANT; DRAIN SOURCE BREAKDOWN VOLTAGE; GATE BIAS; HIGH TEMPERATURE ACTIVATION; HOMOJUNCTION GATE; REFRACTORY METAL GATE CONTACT; SATURATION CURRENT; SILICON SOURCE; TRANSCONDUCTANCE; ZINC IMPLANTATION;

FIELD EFFECT TRANSISTORS;

EID: 0028460271     PISSN: 07413106     EISSN: 15580563     Source Type: Journal    
DOI: 10.1109/55.294083     Document Type: Article

References (10)

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