Modeling the influence of the transistor gain ratio and the input-to-output coupling capacitance on the CMOS inverter delay

IEEE Journal of Solid-State Circuits

Volumn 29, Issue 6, 1994, Pages 646-654

  Jeppson, Kjell O ^a  

^a CHALMERS UNIVERSITY OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; COMPUTER SIMULATION; ELECTRIC INVERTERS; ELECTRIC NETWORK PARAMETERS; FREQUENCY RESPONSE; GAIN CONTROL; GATES (TRANSISTOR); SEMICONDUCTOR DEVICE MODELS; SHORT CIRCUIT CURRENTS; TRANSISTORS; WAVEFORM ANALYSIS;

CMOS INVERTER DELAY; INPUT TO OUTPUT COUPLING CAPACITANCE; TRANSISTOR GAIN RATIO;

CMOS INTEGRATED CIRCUITS;

EID: 0028448787     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.293109     Document Type: Article

References (12)

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