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Volumn 41, Issue 6, 1994, Pages 443-452

Low Control Voltage Programming of Floating Gate MOSFETs and Applications

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER PROGRAMMING; DATA STORAGE EQUIPMENT; FIELD EFFECT TRANSISTORS; GATES (TRANSISTOR); INTEGRATED CIRCUITS; LEARNING SYSTEMS; NEURAL NETWORKS; PROM;

EID: 0028447764     PISSN: 10577122     EISSN: None     Source Type: Journal    
DOI: 10.1109/81.295240     Document Type: Article
Times cited : (12)

References (9)
  • 1
    • 84944812174 scopus 로고
    • A floating gate and its application to memory devices
    • D. Kahng and S. M. Sze, “A floating gate and its application to memory devices,” Bell Syst. Tech. J., vol. 46, p. 1283, 1967.
    • (1967) Bell Syst. Tech. J. , vol.46 , pp. 1283
    • Kahng, D.1    Sze, S.M.2
  • 2
    • 0024737359 scopus 로고
    • The EEPROM as an analog memory device
    • T. C. Ong, P. K. Ko, and C. Hu, “The EEPROM as an analog memory device,” IEEE Trans. Electron. Dev., vol. 36, pp. 1840–1841, 1989.
    • (1989) IEEE Trans. Electron. Dev. , vol.36 , pp. 1840-1841
    • Ong, T.C.1    Ko, P.K.2    Hu, C.3
  • 3
    • 0024910918 scopus 로고
    • Trimming analog circuits using floating-gate analog MOS-memory
    • Dec.
    • L. R. Carley, “Trimming analog circuits using floating-gate analog MOS-memory,” IEEE J. Solid-State Circuits, vol. 24, no. 6, pp. 1569–1575, Dec. 1989.
    • (1989) IEEE J. Solid-State Circuits , vol.24 , Issue.6 , pp. 1569-1575
    • Carley, L.R.1
  • 4
    • 0024122968 scopus 로고
    • An analog trimming circuit based on a floating gate device
    • Dec
    • E. Saeckinger and W. Guggenbuehl, “An analog trimming circuit based on a floating gate device,” IEEE J. Solid State Circuits, vol. 24, pp. 1437–1440, Dec, 1988.
    • (1988) IEEE J. Solid State Circuits , vol.24 , pp. 1437-1440
    • Saeckinger, E.1    Guggenbuehl, W.2
  • 5
    • 0024909727 scopus 로고
    • An electrically trainable artificial neural network (ETANN) with 10240 floating gate synapses
    • M. Holler, S. Tam, H. Castro, and R. Benson, “An electrically trainable artificial neural network (ETANN) with 10240 floating gate synapses,” in Proc. of lnt. Joint Conf. Neural Networks, vol. II, pp. 191–196, 1989.
    • (1989) Proc. of lnt. Joint Conf. Neural Networks , vol.II , pp. 191-196
    • Holler, M.1    Tam, S.2    Castro, H.3    Benson, R.4
  • 6
    • 0026121022 scopus 로고
    • A floating gate MOSFET with tunneling injector fabricated using a standard double polysilicon CMOS process
    • Mar.
    • A. Thomsen and M. A. Brooke, “A floating gate MOSFET with tunneling injector fabricated using a standard double polysilicon CMOS process,” IEEE Electron. Device Lett., vol. 12, no. 3, pp. 111–113, Mar. 1991.
    • (1991) IEEE Electron. Device Lett. , vol.12 , Issue.3 , pp. 111-113
    • Thomsen, A.1    Brooke, M.A.2
  • 7
    • 36849097956 scopus 로고
    • Fowler-Nordheim tunneling into thermally grown SiO2
    • M. Lenzlinger and E. Snow, “Fowler-Nordheim tunneling into thermally grown SiO2,” J. Appl. Phys., vol. 40, pp. 278–283, 1969
    • (1969) J. Appl. Phys. , vol.40 , pp. 278-283
    • Lenzlinger, M.1    Snow, E.2
  • 8
    • 84947660330 scopus 로고
    • High speed high accuracy signal processing with parallel analog circuits
    • Georgia Institute of Technology Dec.
    • A. Thomsen, “High speed high accuracy signal processing with parallel analog circuits,” Ph.D. dissertation, Georgia Institute of Technology, Dec. 1992.
    • (1992) Ph.D. dissertation
    • Thomsen, A.1
  • 9
    • 0004010238 scopus 로고
    • CMOS Analog Circuit Design
    • New York: Holt, Rinehart, and Winston
    • P. Allen and D. Holberg, CMOS Analog Circuit Design. New York: Holt, Rinehart, and Winston, 1987.
    • (1987)
    • Allen, P.1    Holberg, D.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.