Fault models of CMOS circuits

Microelectronics Reliability

Volumn 34, Issue 5, 1994, Pages 883-896

  Milovanović, Dragiša P ^a   Litovski, Vančo B ^a  

^a UNIVERSITY OF NI   (Serbia)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; DEFECTS; FAILURE ANALYSIS;

COMPLEX SEQUENTIAL STRUCTURES; FAULT MODELS; MODEL GENERATION; PATTERN GENERATION;

CMOS INTEGRATED CIRCUITS;

EID: 0028430406     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/0026-2714(94)90012-4     Document Type: Article

References (14)

1. VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits
2. A CMOS fault extractor for inductive fault analysis
3. Modeling faults in digital logic circuits
4. Physical versus logical fault models MOS LSI circuits: impact on their testability
5. Physical failures and fault models of CMOS circuits
6. Physical faults in MOS circuits and their coverage by different fault models
7. MOSSIM A switch-level simulator for MOS LSI
8. Comprehensive fault modeling and simulation in CMOS ICs
9. SPICE2 — a computer program to simulate semiconductor devices
10. Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits
11. Fault models of CMOS transmission gate